There are various kinds of semiconductor products, and innumerable usage patterns are present in all fields. Among others, what has a great ratio is, e.g., a microprocessor (MPU (Micro Processing Unit)) constituted of a MOS (Metal Oxide Semiconductor) transistor, a micro-controller unit (MCU), logic, or a memory. These semiconductor products are mainly applied to a computer, and expansion of this marketplace is greatly dependent on downsizing of a large-scale computing machine to a personal computer, i.e., development of an integrated circuit technology and a reduction in cost.
An improvement in performance and a reduction in cost of a semiconductor product have been achieved in accordance with miniaturization and an increase in a silicon (Si) wafer size, but an increase in size of each device and realization of high performance thereby raise an equipment investment. This increase in equipment cost also raises a product development cost as well as a manufacturing cost, resulting in a circle that is further miniaturization and an increase in a substrate size.
Further, as recent explosive spread and development of mobile phones, a ubiquitous society where a ubiquitous wireless network is provided is to be realized. This is considered as a system in which a terminal integrated circuit chip is embedded in every thing and terminal access system is wirelessly connected with a server through the Internet. A technology required in such a system is further miniaturization and a reduction in power of an existing MOS integrated circuit since a server and a communication system have a high speed and a high capacity. On the other hand, a requirement with respect to a final terminal is downsizing and a reduction in cost.
A CMOS (Complementary Metal Oxide Semiconductor) integrated circuit technology has continued proportional scaling down with a fixed voltage in a period from 1980 to 1995, and a power consumption has consequently quadrupled every year in a 3-year period. Although a power supply voltage has been reduced to suppress this increase, an actual situation is that a good effect cannot be obtained due to miniaturization and high integration.
Besides a reduction in voltage, a reduction in a threshold value of an active device is present as a method of suppressing a power consumption, but this method increases a leak current. These methods are based on fundamental principles of a MOS structure using a Si wafer and, after all, an only solution lies in an architecture, a circuit configuration, and a device operation design.
On the other hand, in a final terminal as typified by an IC tag, an IC section has a relatively simple circuit configuration, but requires a relatively large passive device, e.g., an antenna, an inductor, or a capacitor.
However, when creating a high-frequency passive element of 800 MHz to 5 GHz on a Si wafer, since a silicon substrate has a low resistance, an inductor or the like is coupled with the silicon substrate to reduce Q (quality factor). In case of forming a large capacitor in particular, when the capacitor is to have an on-chip structure, selection of a material becomes difficult, and hence the capacitor is formed on a print-circuit board. As a result, a print-circuit board (PCB) mounting cost is required, and hence a reduction in cost that is a primary requirement of, e.g., an IC tag is difficult.
It is known that most of the above-explained problems can be solved by using a SOI (semiconductor on insulator) substrate. In regard to MOS transistor characteristics, using a fully depleted SOI substrate enables realization of excellent characteristics. Further, using the SOI substrate enables taking various countermeasures for demerits, e.g., a self-heating effect, a substrate floating effect, or a device withstand voltage, and a high-speed logic circuit or a DRAM (dynamic random access memory) is manufactured by way of trial as disclosed in the following Patent Document 1. In a SOI substrate, since an insulating substrate is provided below a semiconductor layer, a high-performance passive device can be also readily formed on a chip.    [Patent Document 1] Japanese Patent Application Publication No. 2004-228206